日時:2015年12月11日(金)13:15~14:45 (13:00より開場) 会場:東京大学情報基盤センター4階遠隔会議室
(会場建物情報) http://www.u-tokyo.ac.jp/campusmap/cam01_13_01_j.html
We are developing a code transformation framework, Xevolver, to allow users to define their own code transformation rules and also to customize typical rules for individual applications and systems. By expressing system-awareness as code transformations, users do not need to directly modify the application code for system-aware performance optimizations. This prevents the application code from being specialized for a particular HPC system, and thereby the application can be expected to achieve high performance portability across system generations. The Xevolver framework uses standard XML technologies to represent code transformations at a low level. In addition, some high-level interfaces and tools for expressing user-defined code transformation rules are now under active development. In this talk, our research activities and some case studies are introduced to discuss the strengths and limitations of our approach to separation of system-awareness from application codes.
As the cost of moving data on current and future architectures becomes increasingly dominant, the challenges of developing high-performance applications are increasingly onerous. The goal of compiler optimization in high-performance computing is to take as input a computation that is architecture independent and maintainable and produce as output efficient implementations of the computation tuned for the target architecture. Autotuning empirically evaluates a search space of possible implementations of a computation to identify the implementation that best meets its optimization criteria (e.g., performance, power, or both). Combining the two concepts, autotuning compilers generate this search space of highly-tuned implementations either automatically or with programmer guidance. This talk will explore the role of compiler technology in achieving very high levels of performance, comparable to what is obtained manually by experts. As a case study, it will highlight some of the aggressive optimizations required to reduce communication for a specific high-performance application domain that is notoriously memory bound: geometric multigrid and the stencil computations within them.
自動チューニング研究会
運営委員会(企画)幹事
東北大学 滝沢寛之
E-mail: takizawa[at]cc.tohoku.ac.jp ([at]を@に置き換えてください)